Wafer failure analysis is the application of failure analysis techniques to determine the cause of yield or performance problems.  Beginning with the failing symptoms, a systematic application of selected failure analysis techniques leads to the cause of failure.  This approach provides key physical data which complements defect reduction and statistical process control programs.  Wafer failure analysis can be conducted by either the manufacturer or by the customer.  Otherwise persistent problems are quickly resolved when both customer and manufacturer understand and cooperate in the analysis.

Failure Analysis Approach

Traditional failure analysis begins after a failure has occurred.  The analyst reviews the history leading up to the failure, verifies and defines the failure mode, then performs various physical tests to establish the failure mechanism and determine the cause of failure.

With slight modification, the same approach can be used to determine the cause(s) of yield loss.  The wafer manufacturer has a detailed history of fabrication and electrical test data.  The IC user has wafer sort data of the actual circuit.  Together, there is enough information to define an accurate failure mode.  After the failure mode is determined, physical analysis techniques can be effectively used to characterize physical properties associated with the failure.  In most cases, once the physics of the failure is understood, the cause of the problem is not hard to find.

A defining element of the failure analysis approach is that determination of the failure mode comes first, followed by physical techniques.  The best analysis techniques cannot determine the cause of an undefined problem.

Even when product test capability is separate from the wafer manufacturer who has analysis responsibility, sufficient characterization of the problem must be completed before the failed material is handed over for analysis.  In some cases, testing must be merged with analysis to precisely identify failure characteristics.  Physical analysis has less chance of success if the failure mode is too general or unknown.

The analysis approach described here incorporates proven problem solving methods championed by Kepner and Tragoe (p85), and by Plunkett and Hale (p31).  Wafer failure analysis, has much in common with problem analysis of Kepner and Tragoe and cause analysis of Plunkett and Hale.  Powerful analysis techniques are a welcome advantage.
Problem Statement

The first step in the failure process is to meaningfully state the problem.  The problem statement is a simple sentence with a subject and a verb.  For example:  “The via chain test structure on four wafers of lot xxx fails electrically open.”  When the failure mode is specific, as for this example, the problem statement serves to focus the analysis around the heart of the problem.

Consider the statement “Wafer sort yield of two lots of product yyy dropped to 54%.”  Neither the heart nor the nature of the problem is contained in this statement.  Meaningful physical analysis cannot begin until further review or additional testing defines the problem.  The most direct path to the cause of the yield drop begins with a closer look at the symptoms of failure.  Questions about “What”, “When”, “Where”, and “How much” must be answered before “Why” questions can be addressed.  Possible questions in the yield problem include: “Compared with the normal percent failure in each fallout bin, which fallout bin(s) account for the increased number of failures?  Are there common differences in parametric data associated with the low yield lots?”   Efforts to sharpen the problem statement save time.  Physical analysis steps are straight forward to determine cause of “Two lots of product yyy show a 250% increase in frequency of IDDQ current fallout at wafer sort.”

Without this first step, time will be wasted on assumed, but non-existent problems.   Imagined causes may even be corrected at great expense.

Subtle problems may require supreme effort to define the problem.  If the problem is too involved to be accurately defined in one sentence, a problem list will serve the same purpose.

Just as a bright area in a painting is highlighted by contrast to surrounding dark areas, the problem statement (or list) is brought into focus by comparison with what might, but is not part of the problem.  To create better focus, it is useful to file comparitive facts in a problem not list.  The list can be either mental or written, depending on complexity of the problem.  This list includes anything that might be expected to share the observed problem, but does not.  It includes expected characteristics that are observed not to exist. Care must be taken to limit the problem and problem not lists to verified facts and observations.  Review both lists for assumptions and exaggerations.  When the lists seem incompatible or impossible, there is a good chance one or more statements is too broad or not exactly true.   Resolution of such incongruities can drive the analysis toward solution.   Critical, but unobserved or unmeasured characteristics must be kept aside in a wonder list.  In one sense, moving questions from the wonder list to either the problem or problem not categories is what analysis is all about.

Verify and Characterize the Failure
When specific failing die or test structures are identified, a curve tracer test may be in order to verify and better understand the failure mode.  The failure statement may be correct, but the symptom identified may not be the most descriptive.  In many cases, automated test equipment (ATE) is the only source of electrical data.  The curve tracer characterization can often attach a meaningful Current/Voltage (I/V) shape to the failure.  Additionally, the valid range of the failure can be explored.  It is easier to locate 10 mA of leakage at 10 volts then to find 3.5 mA at the specified 3.5 volts.

Whenever possible, substitute a basic measurement for the failure mode.  The goal is to find a simple, basic parameter which can be readily monitored with only a few probe pins during deprocessing.

Failure Analysis Procedures
With the failure mode and circumstances now defined, the problem has taken on unique characteristics such that many potential failure mechanisms are ruled out.  There may be strong suspicions about the nature of the failure mechanism, but more than one explanation may seem possible, or none may explain all the observations.

More to the point, the failing characteristics have fixed some boundaries around the problem.  At the same time, other questions have come into focus. Answers to specific questions become important.

Failure analysis procedures offer the possibility of finding answers to questions.   The questions and availability of procedures determine which analysis procedures to choose.  While there is an understandable preference to use procedures available in house, analysts should not be limited to in house procedures.  All the procedures listed below are readily available through outside laboratories. Once the failure is defined as we have discussed, application of the best tools to answer critical specific questions are well worth the expense.

Common failure analysis procedures are listed below:
*  Optical Examination: Microscopic examination at up to 1500x magnification for standard optics, or 3000x for laser confocal optics is used repeatedly throughout an analysis.
*  SEM Examination: Like optical examination, SEM imaging is used throughout an analysis.   Deprocessing and sample preparation steps are key to effective SEM examination.   Additionally, several SEM techniques locate and identify defect sites.
*  Deprocessing: Both chemical and mechanical methods systematically remove or expose layers as required for SEM or other examination.  (Chapter TBD)
*  Resistive Contrast Imaging (RCI) is a simple SEM technique to identify electrically open sites in test structures or in ICs.  One internal probe may be required.   (Chapter TBD)
*  Passive Voltage Contrast (PVC) is a SEM technique for identification of open or leakage sites.  In applicable situations, no internal probes are required.  (Chapter TBD)
*  Mechanical Probing is routinely conducted to electrically characterize a failure by electrical measurement of nodes not otherwise accessible.  (Chapter TBD)
*  Liquid Crystal Hot Spot Detection is a method for locating failure sites that dissipate power.  This procedure can be applied without detailed circuit knowledge.   (Chapter TBD)
*  Emission Microscopy locates sites that emit light within a semiconductor.  Oxide leakage and junctions biased near avalanche can be found by visible light from the topside or, if necessary, through the backside of a wafer or packaged device.  (Chapter TBD)
*  Precision Cross Section: A ninety degree cut through general or specific contacts, vias or other geometries to show details when viewed in a SEM.  (Chapter TBD)
*  EBIC/OBIC are methods to locate junctions or junction damage.  (Chapter TBD)
*  CIVA/LECIVA are SEM techniques for locating electrical opens or near opens.  These techniques are especially powerful on CMOS devices.  (Chapter TBD)
*  Energy Dispersive Xray (EDX) is a material analysis technique to determine the elemental composition of features or films.  (Chapter TBD)
*  Auger, ESCA, and SIMS are surface analysis tools.  (Chapter TBD)

End Notes
C Kepner, B Tregoe, The Rational Manager, McGraw-Hill Book Co., 1965
L Plunkett, G Hale, The Proactive Manager, John Wiley and Sons, 1982

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