Dave Burgess is working through Accelerated Analysis to make his more than 35 years experience in failure analysis and reliability physics available to semiconductor users and manufacturers. For nearly 15 years, he was responsible for training and development of Hewlett-Packard’s failure analysis capability. He continues to conduct semiconductor failure analysis for companies in Silicon Valley.
Dave understands that efficient failure analysis depends on unique application of common tools as well as availability of unique tools designed exclusively for failure analysis. He is co-author with Dr Richard A Blanchard of “Wafer Failure Analysis,” a text addressing the whole failure analysis process, including thought, technique, and technology. David has several patents in failure analysis tools for cross sectioning and liquid crystal analysis.
He has authored papers and served active roles at both ISTFA (International Symposium for Testing and Failure Analysis) and at IRPS (International Reliability Physics Symposium). He is past general chairman of IRPS and an active member of EDFAS, the Electronic Device Failure Analysis Society.
Dave received a BEE from Rensselaer Polytechnic Institute and an MSEE degree from San Jose State University.